SPP4925B
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP4925B is the Dual P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application , notebook computer power management and
other battery powered circuits where high-side
switching .
FEATURES
-30V/-7.2A,R
DS(ON)
= 24mΩ@V
GS
=- 10V
-30V/-5.6A,R
DS(ON)
= 30mΩ@V
GS
=-4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOP – 8P package design
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
PIN CONFIGURATION(SOP – 8P)
PART MARKING
2009/03/20
Ver.1
Page 1
SPP4925B
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Symbol
S1
G1
S2
G2
D2
D2
D1
D1
Description
Source 1
Gate 1
Source 2
Gate 2
Drain 2
Drain 2
Drain 1
Drain 1
ORDERING INFORMATION
Part Number
SPP4925BS8RGB
Package
SOP- 8P
Part
Marking
SPP4925B
※
SPP4925BS8RGB : 13” Tape Reel ; Halogen – Free ; Pb – Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-30
±20
Unit
V
V
A
A
A
W
℃
℃
℃/W
-7.2
-5.6
-20
-2.3
2.8
1.8
-55/150
-55/150
70
2009/03/20
Ver.1
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SPP4925B
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25℃ Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DD
=-15V,R
L
=15Ω
I
D
≡-1.0A,V
GEN
=-10V
R
G
=6Ω
V
DS
=-15V,V
GS
=0V
f=1MHz
V
DS
=0V,V
GS
=±20V
V
DS
=-24V,V
GS
=0V
V
DS
=-24V,V
GS
=0V
T
J
=85℃
V
DS
= -5V,V
GS
=-4.5V
V
GS
=-10V,I
D
=-9.2A
V
GS
=-4.5V,I
D
=-7.0A
V
DS
=-10V,I
D
=-9.0A
I
S
=-2.3A,V
GS
=0V
-30
-0.7
-1.6
±100
-1
-5
-40
0.020
0.024
24
-0.8
20
3.5
4.8
1850
450
335
20
20
75
40
30
30
110
80
0.024
0.030
-1.2
30
V
nA
uA
A
Ω
S
V
V
DS
=-15V,V
GS
=-10V
I
D
= -9.0A
nC
pF
nS
2009/03/20
Ver.1
Page 3
SPP4925B
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2009/03/20
Ver.1
Page 4
SPP4925B
P-Channel Enhancement Mode MOSFET
TYPICAL CHARACTERISTICS
2009/03/20
Ver.1
Page 5
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